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september 2009 doc id 10367 rev 8 1/33 1 m34e02 2 kbit serial presence detect (spd) eeprom for double data rate (ddr 1 and ddr2) dram modules features 2 kbit eeprom for ddr1 and ddr2 serial presence detect backward compatible with the m34c02 permanent and reversible software data protection for lower 128 bytes 100 khz and 400 khz i 2 c bus serial interface single supply voltage: ? 1.7 v to 5.5 v byte and page write (up to 16 bytes) self-timed write cycle noise filtering ? schmitt trigger on bus inputs ? noise filter on bus inputs enhanced esd/latch-up protection more than 1 million erase/write cycles more than 40 years? data retention ecopack ? (rohs compliant) packages tssop8 (dw) 4.4 3 mm ufdfpn8 (mb) 2 3 mm (mlp) www.st.com
contents m34e02 2/33 doc id 10367 rev 8 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 chip enable (e0, e1, e2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 write control (wc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5.1 operating supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5.3 device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5.4 power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.5 memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.6 setting the write-protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6.1 swp and cwp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6.2 pswp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.7 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7.2 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7.3 minimizing system delays by polling on ack . . . . . . . . . . . . . . . . . . . . . 16 3.8 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8.1 random address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8.2 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8.3 sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8.4 acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
m34e02 contents doc id 10367 rev 8 3/33 5 use within a ddr1/ddr2 dram module . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 programming the m34e02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.1 isolated dram module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.2 dram module inserted in the application motherboard . . . . . . . . . . . . 19 6 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
list of tables m34e02 4/33 doc id 10367 rev 8 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4. dram dimm connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. acknowledge when writing data or defining the write-protection (instructions with r/w bit = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6. acknowledge when reading the write protection (instructions with r/w bit = 1). . . . . . . . . 20 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8. operating conditions (for temperature range 1 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 9. operating conditions (for temperature range 6 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11. input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 12. dc characteristics (for temperature range 1 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 13. dc characteristics (for temperature range 6 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 14. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 15. ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2 3 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 16. tssop8 ? 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 29 table 17. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 18. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
m34e02 list of figures doc id 10367 rev 8 5/33 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. tssop and mlp connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. maximum r p value versus bus parasitic capacitance (c) for an i 2 c bus . . . . . . . . . . . . . . . 9 figure 5. i 2 c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. result of setting the write protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. setting the write protection (wc = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8. write mode sequences in a non write-protected area . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 9. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 figure 10. read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 11. serial presence detect block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 13. ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 14. ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2 3 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 15. tssop8 ? 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 29
description m34e02 6/33 doc id 10367 rev 8 1 description the m34e02 is a 2 kbit serial eeprom memory able to lock permanently the data in its first half (from location 00h to 7fh). this facility has been designed specifically for use in dram dimms (dual interline memory modules) with serial presence detect (spd). all the information concerning the ddr1 or ddr2 configuration of the dram module (such as its access speed, size and organization) can be kept write-protected in the first half of the memory. the first half of the memory area can be write-protected using two different software write protection mechanisms. by sending the device a specific sequence, the first 128 bytes of the memory become write protected: permanently or resettable. in addition, the device allows the entire memory area to be write protected, using the wc input (for example by tieing this input to v cc ). these i 2 c-compatible electrically erasable pr ogrammable memory (eeprom) devices are organized as 256 8 bits. i 2 c uses a two wire serial interface, comprising a bi-directional data line and a clock line. the device carries a built-in 4-bit device type identifier code (1010) in accordance with the i 2 c bus definition to access the memory area and a second device type identifier code (0110) to define the protection. these codes are used together with the voltage level applied on the three chip enable inputs (e2, e1, e0). the device behaves as a slave device in the i 2 c protocol, with all memory operations synchronized by the serial clock. read and write operations are initiated by a start condition, generated by the bus master. the start condition is followed by a device select code and rw bit (as described in ta b l e 2 ), terminated by an acknowledge bit. when writing data to the memory, the memory inserts an acknowledge bit during the 9 th bit time, following the bus master?s 8-bit transmission. when data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. data transfers are terminated by a stop condition after an ack for write, and after a noack for read. figure 1. logic diagram ai09020 3 e0-e2 sda v cc m34e02 wc scl v ss
m34e02 description doc id 10367 rev 8 7/33 figure 2. tssop and mlp connections (top view) 1. see the package mechanical data section for package dimensions, and how to identify pin-1. table 1. signal names signal names description e0, e1, e2 chip enable sda serial data scl serial clock wc write control v cc supply voltage v ss ground sda v ss scl wc e1 e0 v cc e2 ai09021 m34e02 1 2 3 4 8 7 6 5
signal description m34e02 8/33 doc id 10367 rev 8 2 signal description 2.1 serial clock (scl) this input signal is used to strobe all data in and out of the device. in applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor can be connected from serial clock (scl) to v cc . ( figure 4 indicates how the value of the pull-up resistor can be calculated). in most applications, though, this method of sy nchronization is not employed, and so the pull- up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. 2.2 serial data (sda) this bidirectional signal is used to transfer data in or out of the device. it is an open drain output that may be wire-or?ed with other open drain or open collector signals on the bus. a pull up resistor must be connected from serial data (sda) to v cc . ( figure 4 indicates how the value of the pull-up resistor can be calculated). 2.3 chip enable (e0, e1, e2) these input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. in the end application, e0, e1 and e2 must be directly (not through a pull-up or pull-down resistor) connected to v cc or v ss to establish the device select code. when these inputs are not connected, an internal pull- down circuitry makes (e0,e1,e2) = (0,0,0). the e0 input is used to detect the v hv voltage, when decoding an swp or cwp instruction. figure 3. device select code 2.4 write control (wc ) this input signal is provided for protecting the contents of the whole memory from inadvertent write operat ions. write control (wc ) is used to enable (when driven low) or disable (when driven high) write instructions to the entire memory area or to the protection register. when write control (wc ) is tied low or left unconnected, the write protection of the first half of the memory is determined by the status of the protection register. ai12301 v cc m34e02 v ss e i v cc m34e02 v ss e i
m34e02 signal description doc id 10367 rev 8 9/33 2.5 supply voltage (v cc ) 2.5.1 operating supply voltage v cc prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see ta bl e 8 ). in order to secure a stable dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the v cc /v ss package pins. this voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (t w ). 2.5.2 power-up conditions the v cc voltage has to rise continuously from 0 v up to the minimum v cc operating voltage defined in ta bl e 8 and the rise time must not vary faster than 1 v/s. 2.5.3 device reset in order to prevent inadvertent write operations during power-up, a power-on reset (por) circuit is included. at power-up, the device does not respond to any instruction until v cc reaches the internal reset threshold voltage (this threshold is lower than the minimum v cc operating voltage defined in ta b l e 8 ). when v cc passes over the por threshold, the device is reset and enters the standby power mode. however, the device must not be accessed until v cc reaches a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range. in a similar way, during power-down (continuous decrease in v cc ), as soon as v cc drops below the power-on reset threshold voltage, the device stops responding to any instruction sent to it. 2.5.4 power-down conditions during power-down (continuous decrease in v cc ), the device must be in standby power mode (mode reached after decoding a stop cond ition, assuming that there is no internal write cycle in progress). figure 4. maximum r p value versus bus parasitic capacitance (c) for an i 2 c bus 1 10 100 10 100 1000 b us line c a p a citor (pf) b us line p u ll- u p re s i s tor (k ) when t low = 1. 3 s (min v a l u e for f c = 400 khz), the r bus c bus time con s t a nt m us t b e b elow the 400 n s time con s t a nt line repre s ented on the left. i2c bus m as ter m24xxx r bus v cc c bus s cl s da a i14796 b r bus c bus = 400 n s here r bus c bus = 120 n s 4 k 3 0 pf
signal description m34e02 10/33 doc id 10367 rev 8 figure 5. i 2 c bus protocol table 2. device select code chip enable signals device type identifier chip enable bits rw b7 (1) 1. the most significant bit, b7, is sent first. b6 b5 b4 b3 b2 b1 b0 memory area select code (two arrays) (2) 2. e0, e1 and e2 are compared against the respec tive external pins on the memory device. e2 e1 e0 1 0 1 0 e2 e1 e0 rw set write protection (swp) v ss v ss v hv (3) 3. v hv is defined in table 13 . 0110 0010 clear write protection (cwp) v ss v cc v hv (3) 0110 permanently set write protection (pswp) (2) e2 e1 e0 e2 e1 e0 0 read swp v ss v ss v hv (3) 0011 read cwp v ss v cc v hv (3) 0111 read pswp (2) e2 e1 e0 e2 e1 e0 1 scl sda scl sda sda start condition sda input sda change ai00792c stop condition 1 23 7 89 msb ack start condition scl 1 23 7 89 msb ack stop condition
m34e02 device operation doc id 10367 rev 8 11/33 3 device operation the device supports the i 2 c protocol. this is summarized in figure 5 any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. the device that controls the data transfer is known as the bus master, and the other as the slave device. a data transfer can on ly be initiated by the bus master, which will also provide the serial clock for synchronization . the memory device is always a slave in all communication. 3.1 start condition start is identified by a falling edge of serial da ta (sda) while serial clock (scl) is stable in the high state. a start condition must precede any data transfer command. the device continuously monitors (except during a write cycle) serial data (sda) and serial clock (scl) for a start condition, and will not respond unless one is given. 3.2 stop condition stop is identified by a rising edge of serial data (sda) while serial clock (scl) is stable and driven high. a stop condition terminates communication between the device and the bus master. a read command that is followed by noack can be followed by a stop condition to force the device into the standby mode. a stop condition at the end of a write command triggers the internal eeprom write cycle. 3.3 acknowledge bit (ack) the acknowledge bit is used to indicate a successful byte transfer. the bus transmitter, whether it be bus master or slave device, releases serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls serial data (sda) low to acknowledge the receipt of the eight data bits. 3.4 data input during data input, the device samples serial data (sda) on the rising edge of serial clock (scl). for correct device operation, serial data (sda) must be stable during the rising edge of serial clock (scl), and the serial data (sda) signal must change only when serial clock (scl) is driven low.
device operation m34e02 12/33 doc id 10367 rev 8 3.5 memory addressing to start communication between the bus master and the slave device, the bus master must initiate a start condition. follo wing this, the bus master sends the device select code, shown in ta b l e 2 (on serial data (sda), most significant bit first). the device select code consists of a 4-bit device type identifier, and a 3-bit chip enable ?address? (e2, e1, e0). to address the memory array, the 4-bit device type identifier is 1010b; to access the write-protection settings, it is 0110b. up to eight memory devices can be connected on a single i 2 c bus. each one is given a unique 3-bit code on the chip enable (e0, e1, e2) inputs. when the device select code is received, the device only responds if the chip enable address is the same as the value on the chip enable (e0, e1, e2) inputs. the 8 th bit is the read/write bit (rw ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the device does not match the device select code, it deselects itself from the bus, and goes into standby mode. figure 6. result of setting the write protection table 3. operating modes mode rw bit wc (1) 1. x = v ih or v il . bytes initial sequence current address read 1 x 1 s tart, device select, rw = 1 random address read 0x 1 start, device select, rw = 0, address 1 x restart, device select, rw = 1 sequential read 1 x ? 1 similar to current or random address read byte write 0 v il 1 start, device select, rw = 0 page write 0 v il ?? 16 start, device select, rw = 0 default eeprom memory area state before write access to the protect register ai01936c standard array ffh standard array 80h 7fh 00h standard array ffh write protected array 80h 7fh 00h state of the eeprom memory area after write access to the protect register memory area
m34e02 device operation doc id 10367 rev 8 13/33 3.6 setting the write-protection the m34e02 has a hardware write-protection feature, using the write control (wc ) signal. this signal can be driven high or low, and must be held constant for the whole instruction sequence. when write control (wc ) is held high, the whole memory array (addresses 00h to ffh) is write protected. when write control (wc ) is held low, the write protection of the memory array is dependent on whether software write-protection has been set. software write-protection allows the bottom half of the memory area (addresses 00h to 7fh) to be write protected irrespective of subsequent states of the write control (wc ) signal. software write-protection is handled by three instructions: swp: set write protection cwp: clear write protection pswp: permanently set write protection the level of write-protection (set or cleared) that has been defined using these instructions, remains defined even after a power cycle. 3.6.1 swp and cwp if the software write-protection has been set with the swp instruction, it can be cleared again with a cwp instruction. the two instructions (swp and cwp) have the same format as a byte write instruction, but with a different device type identifier (as shown in ta bl e 2 ). like the byte write instruction, it is followed by an address byte and a data byte, but in this case the contents are all ?don?t care? ( figure 7 ). another difference is that the voltage, v hv , must be applied on the e0 pin, and specific logical levels must be applied on the other two (e1 and e2, as shown in ta bl e 2 ). 3.6.2 pswp if the software write-protection has been set with the pswp instruction, the first 128 bytes of the memory are permanently write-protected. this write-protection cannot be cleared by any instruction, or by power-cycling the device, and regardless the state of write control (wc ). also, once the pswp instruction has been successfully executed, the m34e02 no longer acknowledges any instruction (with a device type identifier of 0110) to access the write-protection settings. figure 7. setting the write protection (wc = 0) start sda line ai01935b ack word address value (don't care) ack data value (don't care) stop ack control byte bus activity master bus activity
device operation m34e02 14/33 doc id 10367 rev 8 3.7 write operations following a start condition the bus master sends a device select code with the rw bit reset to 0. the device acknowledges this, as shown in figure 8 , and waits for an address byte. the device responds to the address byte with an acknowledge bit, and then waits for the data byte. when the bus master generates a stop condition immediately after the ack bit (in the ?10 th bit? time slot), either at the end of a byte write or a page write, the internal memory write cycle is triggered. a stop condition at any other time slot does not trigger the internal write cycle. during the internal write cycle, serial data (sda) and serial clock (scl) are ignored, and the device does not respond to any requests. 3.7.1 byte write after the device select code and the address byte, the bus master sends one data byte. if the addressed location is hardware write-protected, the device replies to the data byte with noack, and the location is not modified. if, instead, the addressed location is not write- protected, the device replies with ack. the bus master terminates the transfer by generating a stop condition, as shown in figure 8 3.7.2 page write the page write mode allows up to 16 bytes to be written in a single write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits are the same. if more byte s are sent than will fit up to the end of the page, a condition known as ?roll-over? occurs. this should be avoided, as data starts to become overwritten in an implementation dependent way. the bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device if write control (wc ) is low. if the addressed location is hardware write-protected, the device replies to the data byte with noack, and the locations are not modified. after each byte is transferred, the internal byte address counter (the 4 least significant address bits only) is incremented. the transfer is terminated by the bus master generating a stop condition.
m34e02 device operation doc id 10367 rev 8 15/33 figure 8. write mode sequences in a non write-protected area figure 9. write cycle polling flowchart using ack stop start byte write device select byte address data in start page write device select byte address data in 1 data in 2 ai01941b stop data in n ack ack ack r/w ack ack ack r/w ack ack write cycle in progress ai01847d next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop data for the write operation device select with rw = 1 send address and receive ack first byte of instruction with rw = 0 already decoded by the device yes no start condition continue the write operation continue the random read operation
device operation m34e02 16/33 doc id 10367 rev 8 3.7.3 minimizing system delays by polling on ack during the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. the maximum write time (t w ) is shown in ta b l e 1 4 , but the typical time is shorter. to make use of this, a polling sequence can be used by the bus master. the sequence, as shown in figure 9 , is: initial condition: a write cycle is in progress. step 1: the bus master issues a start condition followed by a device select code (the first byte of the new instruction). step 2: if the device is busy with the inte rnal write cycle, no ack will be returned and the bus master goes back to step 1. if the device has terminated the internal write cycle, it responds with an ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). 3.8 read operations read operations are performed independently of whether hardware or software protection has been set. the device has an internal address counter which is incremented each time a byte is read. 3.8.1 random address read a dummy write is first performed to load the address into this address counter (as shown in figure 10 ) but without sending a stop condition. then, the bus master sends another start condition, and repeats the device select code, with the rw bit set to 1. the device acknowledges this, and outputs the contents of the addressed byte. the bus master must not acknowledge the byte, and terminates the transfer with a stop condition. 3.8.2 current address read for the current address read operation, following a start condition, the bus master only sends a device sele ct code with the rw bit set to 1. the device acknowledges this, and outputs the byte addressed by the internal address counter. the counter is then incremented. the bus master terminates the transfer with a stop condition, as shown in figure 10 , without acknowledging the byte. 3.8.3 sequential read this operation can be used after a current address read or a random address read. the bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 10 . the output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. after the last memory address, the address counter ?rolls-over?, and the device continues to output data from memory address 00h.
m34e02 device operation doc id 10367 rev 8 17/33 3.8.4 acknowledg e in read mode for all read commands, the device waits, after each byte read, for an acknowledgment during the 9 th bit time. if the bus master does not drive serial data (sda) low during this time, the device terminates the data transfer and switches to its standby mode. figure 10. read mode sequences 1. the seven most significant bits of the dev ice select code of a random read (in the 1 st and 3 rd bytes) must be identical. start dev select * byte address start dev select data out 1 ai01942b data out n stop start current address read dev select data out random address read stop start dev select * data out sequential current read stop data out n start dev select * byte address sequential random read start dev select * data out 1 stop ack r/w no ack ack r/w ack ack r/w ack ack ack no ack r/w no ack ack ack r/w ack ack r/w ack no ack
initial delivery state m34e02 18/33 doc id 10367 rev 8 4 initial delivery state the device is delivered with all bits in the memory array set to ?1? (each byte contains ffh). 5 use within a ddr1/ddr2 dram module in the application, the m34e02 is soldered directly in the printed circuit module. the three chip enable inputs (e0, e1, e2) must be connected to v ss or v cc directly (that is without using a pull-up or pull-down resistor) through the dimm socket (see ta b l e 4 ). the pull-up resistors needed for normal behavior of the i 2 c bus are connected on the i 2 c bus of the mother-board (as shown in figure 11 ). the write control (wc ) of the m34e02 can be left unconnected. however, connecting it to v ss is recommended, to maintain full read and write access. 5.1 programming the m34e02 the situations in which the m34e02 is programmed can be considered under two headings: when the ddr2 dram is isolated (not inserted on the pcb motherboard) when the ddr2 dram is inserted on the pcb motherboard 5.1.1 isolated dram module with specific programming equipment, it is possible to define the m34e02 content, using byte and page write instructions, and its write-protection using the swp and cwp instructions. to issue the swp and cwp instructions, the dram module must be inserted in a specific slot where the e0 signal can be driven to v hv during the whole instruction. this programming step is mainly intended for use by dram module makers, whose end application manufacturers will want to clear th is write-protection with the cwp on their own specific programming equipment, to modify the lower 128 bytes, and finally to set permanently the write-protection with the pswp instruction. table 4. dram dimm connections dimm position e2 e1 e0 0 v ss v ss v ss 1 v ss v ss v cc 2 v ss v cc v ss 3 v ss v cc v cc 4 v cc v ss v ss 5 v cc v ss v cc 6 v cc v cc v ss 7 v cc v cc v cc
m34e02 use within a ddr1/ddr2 dram module doc id 10367 rev 8 19/33 5.1.2 dram module inserted in the application motherboard as the final application cannot drive the e0 pin to v hv , the only possible action is to freeze the write-protection with the pswp instruction. ta bl e 5 and ta bl e 6 show how the ack bits can be used to identify the write-protection status. table 5. acknowledge when writing data or defining the write-protection (instructions with r/w bit = 0) status wc input level instruction ack address ack data byte ack write cycle (t w ) permanently protected x pswp, swp or cwp noack not significant noack not significant noack no page or byte write in lower 128 bytes ack address ack data noack no protected with swp swp noack not significant noack not significant noack no cwp ack not significant ack not significant ack ye s 0 pswp ack not significant ack not significant ack ye s page or byte write in lower 128 bytes ack address ack data noack no swp noack not significant noack not significant noack no 1 cwp ack not significant ack not significant noack no pswp ack not significant ack not significant noack no page or byte write ack address ack data noack no not protected 0 pswp, swp or cwp ack not significant ack not significant ack ye s page or byte write ack address ack data ack ye s 1 pswp, swp or cwp ack not significant ack not significant noack no page or byte write ack address ack data noack no
use within a ddr1/ ddr2 dram module m34e02 20/33 doc id 10367 rev 8 table 6. acknowledge when reading the write protection (instructions with r/w bit = 1) status instruction ack address ack data byte ack permanently protected pswp, swp or cwp noack not significant noack not significant noack protected with swp swp noack not significant noack not significant noack cwp ack not significant noack not significant noack pswp ack not significant noack not significant noack not protected pswp, swp or cwp ack not significant noack not significant noack
m34e02 use within a ddr1/ddr2 dram module doc id 10367 rev 8 21/33 figure 11. serial presence detect block diagram 1. e0, e1 and e2 are wired at each dram module slot in a binary sequence for a maximum of 8 devices. 2. common clock and common data are shared across all the devices. r = 4.7 k ai01937b dram module slot number 7 sda scl e0 e1 e2 v cc dram module slot number 6 sda scl e0 e1 e2 dram module slot number 5 sda scl e0 e1 e2 dram module slot number 4 sda scl e0 e1 e2 dram module slot number 3 sda scl e0 e1 e2 dram module slot number 2 sda scl e0 e1 e2 v cc dram module slot number 1 sda scl e0 e1 e2 dram module slot number 0 sda scl e0 e1 e2 v ss v ss v ss v cc v ss v ss v cc v cc v ss v cc v cc v ss v ss v cc scl line sda line from the motherboard i 2 c master controller
maximum rating m34e02 22/33 doc id 10367 rev 8 6 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 7. absolute maximum ratings symbol parameter min. max. unit t stg storage temperature ?65 150 c v io input or output range e0 others ?0.50 ?0.50 10.0 6.5 v i ol dc output current (sda = 0) - 5 ma v cc supply voltage ?0.5 6.5 v v esd electrostatic discharge voltage (human body model) (1) 1. jedec std jesd22-a114a (c1=100 pf, r1=1500 ? , r2=500 ? ) ?4000 4000 v
m34e02 dc and ac parameters doc id 10367 rev 8 23/33 7 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. figure 12. ac measurement i/o waveform table 8. operating conditions (for temperature range 1 devices) symbol parameter min. max. unit v cc supply voltage 1.7 3.6 v t a ambient operating temperature 0 70 c table 9. operating conditions (for temperature range 6 devices) symbol parameter min. max. unit v cc supply voltage 1.7 5.5 v t a ambient operating temperature ?40 +85 c table 10. ac measurement conditions symbol parameter min. max. unit c l load capacitance 100 pf input rise and fall times 50 ns input levels 0.2v cc to 0.8v cc v input and output timing reference levels 0.3v cc to 0.7v cc v ai00825b 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels
dc and ac parameters m34e02 24/33 doc id 10367 rev 8 table 11. input parameters symbol parameter (1) 1. characterized, not tested in production. test condition min . max . unit c in input capacitance (sda) 8 pf c in input capacitance (other pins) 6 pf z eil ei (e0, e1, e2) input impedance v in < 0.3v cc 30 k ? z eih ei (e0, e1, e2) input impedance v in > 0.7v cc 800 k ? z wcl wc input impedance v in < 0.3v cc 5k ? z wch wc input impedance v in > 0.7v cc 500 k ? t ns pulse width ignored (input filter on scl and sda) 100 ns table 12. dc characteristics (for temperature range 1 devices) symbol parameter test condition (in addition to those in table 8 ) min max unit i li input leakage current (scl, sda) v in = v ss or v cc 2 a i lo output leakage current v out = v ss or v cc, sda in hi-z 2 a i cc supply current (read) v cc = 1.7 v, f c = 100 khz (rise/fall time < 50 ns) 1ma v cc = 3.6 v, f c = 100 khz (rise/fall time < 50 ns) 2ma i cc1 standby supply current v in = v ss or v cc , v cc = 3.6 v 2 a v in = v ss or v cc , v cc = 1.7 v 1 a v il input low voltage (scl, sda, wc ) 2.5 ? v cc ?0.45 0.3 v cc v 1.7 v ? v cc < 2.5 v ?0.45 0.25v cc v v ih input high voltage (scl, sda, wc ) 0.7v cc v cc +1 v v hv e0 high voltage v hv ? v cc ? 4.8 v 7 10 v v ol output low voltage i ol = 2.1 ma, 2.2 v ? v cc ? 3.6 v 0.4 v i ol = 0.7 ma, v cc = 1.7 v 0.2 v
m34e02 dc and ac parameters doc id 10367 rev 8 25/33 table 13. dc characteristics (for temperature range 6 devices) symbol parameter test condition (in addition to those in table 9 ) min max unit i li input leakage current (scl, sda) v in = v ss or v cc 2 a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc 2 a i cc supply current (read) v cc < 2.5 v, f c = 400 khz (rise/fall time < 50 ns) 1ma v cc ? 2.5 v, f c = 400 khz (rise/fall time < 50 ns) 3ma i cc1 standby supply current device not selected (1) , v in = v ss or v cc , v cc ? 2.5 v 1. the device is not selected after a power-up, after a read command (after the stop condition), or after the completion of the internal write cycle t w (t w is triggered by the correct decoding of a write command). 2a device not selected (1) , v in = v ss or v cc , v cc < 2.5 v 1a v il input low voltage (scl, sda, wc ) 2.5 ? v cc ?0.45 0.3 v cc v 1.8 v ? v cc < 2.5 v ?0.45 0.25v cc v v ih input high voltage (scl, sda, wc ) 0.7v cc v cc +1 v v hv e0 high voltage v hv ? v cc ? 4.8 v 7 10 v v ol output low voltage i ol = 3.0 ma, v cc = 5.5 v 0.4 v i ol = 2.1 ma, v cc = 2.5 v 0.4 v i ol = 0.7 ma, v cc = 1.7 v 0.2 v
dc and ac parameters m34e02 26/33 doc id 10367 rev 8 table 14. ac characteristics test conditions specified in table 10 , table 8 and table 9 symbol alt. parameter min. max. unit f c f scl clock frequency 400 khz t chcl t high clock pulse width high 600 ns t clch t low clock pulse width low 1300 ns t dl1dl2 (1) 1. sampled only, not 100% tested. t f sda (out) fall time 20 100 ns t xh1xh2 (2) 2. values recommended by i2c- bus/fast-mode specification. t r input signal rise time 20 300 ns t xl1xl2 (2) t f input signal fall time 20 300 ns t dxcx t su:dat data in set up time 100 ns t cldx t hd:dat data in hold time 0 ns t clqx t dh data out hold time 200 ns t clqv (3) 3. to avoid spurious start and stop conditions, a minimum delay is pl aced between scl=1 and the falling or rising edge of sda. t aa clock low to next data valid (access time) 200 900 ns t chdl (4) 4. for a re-start condition, or following a write cycle. t su:sta start condition setup time 600 ns t dlcl t hd:sta start condition hold time 600 ns t chdh t su:sto stop condition setup time 600 ns t dhdl t buf time between stop condition and next start condition 1300 ns t w t wr write time 5 ms
m34e02 dc and ac parameters doc id 10367 rev 8 27/33 figure 13. ac waveforms scl sda in scl sda out scl sda in tchcl tdlcl tchdx start condition tclch tdxcx tcldx sda input sda change tchdh tdhdl stop condition data valid tclqv tclqx tchdh stop condition tchdx start condition write cycle tw ai00795e start condition tchcl txh1xh2 txh1xh2 txl1xl2 txl1xl2 data valid tdl1dl2
package mechanical data m34e02 28/33 doc id 10367 rev 8 8 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 14. ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2 3 mm, package outline 1. drawing is not to scale. 2. the central pad (the area e2 by d2 in the abov e illustration) is pulle d, internally, to v ss . it must not be connected to any other voltage or signal line on the pcb, for example during the soldering process. 3. the circle in the top view of the package indicates the position of pin 1. table 15. ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2 3 mm, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ min max typ min max a 0.550 0.450 0.600 0.0217 0.0177 0.0236 a1 0.020 0.000 0.050 0.0008 0.0000 0.0020 b 0.250 0.200 0.300 0.0098 0.0079 0.0118 d 2.000 1.900 2.100 0.0787 0.0748 0.0827 d2 1.600 1.500 1.700 0.0630 0.0591 0.0669 e 3.000 2.900 3.100 0.1181 0.1142 0.1220 e2 0.200 0.100 0.300 0.0079 0.0039 0.0118 e 0.500 - - 0.0197 - - l 0.450 0.400 0.500 0.0177 0.0157 0.0197 l1 0.150 0.0059 l3 0.300 0.0118 ddd (2) 2. applied for exposed die paddle and terminals. exclude embedding part of exposed die paddle from measuring. 0.080 0.0031 d e ufdfpn-01 a a1 ddd l1 e b d2 l e2 l3
m34e02 package mechanical data doc id 10367 rev 8 29/33 figure 15. tssop8 ? 8-lead thin shrink small outline, package outline 1. drawing is not to scale. 2. the circle around the number 1 in the top view of the package indicates the position of pin 1. the numbers 4, 5 and 8 indicate the positions of pins 4, 5 and 8, respectively. table 16. tssop8 ? 8-lead thin shrink small outline, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ. min. max. typ. min. max. a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 ? ? 0.0256 ? ? e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 0.0394 ? 0 8 0 8 n8 8 tssop8am 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1
part numbering m34e02 30/33 doc id 10367 rev 8 9 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 17. ordering information scheme example: m34e02 ? f dw 1 t p device type m34 = assp i 2 c serial access eeprom device function e02 = 2 kbit (256 8) spd (serial presence detect) for ddr1 and ddr2 operating voltage f = v cc = 1.7 to 3.6 v over 0c to 70 c (1) or 1. the 1.7 to 3.6 v operating voltage range is available only on temper ature range 1 devices. f = v cc = 1.7 to 5.5 v over ?40 c to 85 c (2) 2. the 1.7 to 5.5 v operating voltage range is available only on temper ature range 6 devices. package mb = udfdfpn8 (mlp8) dw = tssop8 (4.4 3 mm body size) temperature range 1 = 0 to 70 c 6 = ?40 to 85 c option blank = standard packing t = tape & reel packing plating technology p or g = ecopack (rohs compliant)
m34e02 revision history doc id 10367 rev 8 31/33 10 revision history table 18. document revision history date revision changes 13-nov-2003 1.0 first release 01-dec-2003 1.1 tssop8 4.4x3 package replaces tssop8 3x3 (msop8) package. correction to sentence in ?setting the write protection?. correction to specification of t ns values. 29-mar-2004 1.2 always noack after address and data bytes in ta b l e 6 . improvement in v io and v cc (min) in absolute maximum ratings table. i ol changed for test condition of v ol . mlp package mechanical data respecified. soldering temperature information clarified for rohs compliant devices. 14-apr-2004 2.0 first public release 24-nov-2004 3.0 direct connection of e0, e1, e2 to v ss and v cc (see chip enable (e0, e1, e2) and use within a ddr1/ddr2 dram module paragraphs). z eil and z eih parameters added to table 11: input parameters . e0, e1, e2 removed from the parameter descriptions of v il and v ih in table 13: dc characteristics (for temperature range 6 devices) . document status promoted from product preview to full datasheet. 11-mar-2005 4.0 datasheet title changed. features revised. plating technology options updated in table 17: ordering information scheme . resistance and capacitance renamed in figure 4: maximum rp value versus bus parasitic capacitance (c) for an i2c bus . 28 -apr-2005 5.0 text in power on reset changed. noise filter value in table 11: input parameters modified. i cc value 2ma, when vcc=3/6v, added to table 13: dc characteristics (for temperature range 6 devices) . 10-apr-2006 6 in table 14: ac characteristics : frequency f c changed from 100khz to 400khz, related ac timings (t chcl , t clch , t dxcx , t clqv max, t chdx , t dlcl , t chdh , t dhdl ) also modified. power on reset paragraph removed replaced by internal device reset . figure 3: device select code inserted. i cc1 modified in table 13: dc characteristics (for temperature range 6 devices) . note 3 added to figure 14 and note 2 added to figure 15 all packages are ecopack? (see text added under description and part numbering , t lead removed from table 7: absolute maximum ratings ).
revision history m34e02 32/33 doc id 10367 rev 8 18-mar-2009 7 datasheet title and features on page 1 modified: the device can be used with ddr1 and ddr2 dram configurations. temperature range 6 added, operating voltage range v cc extended in device temperature range 6. i ol added to and t a modified in ta bl e 7 : absolute maximum ratings . i lo , i cc and v il modified in table 13: dc characteristics (for temperature range 6 devices) . table 14: ac characteristics added. table 13: dc characteristics (for temperature range 6 devices) modified. figure 13: ac waveforms modified. figure 4: maximum rp value versus bus parasitic capacitance (c) for an i2c bus updated. note removed below figure 11: serial presence detect block diagram . ufdfpn8 package specifications updated (see table 15: ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2 3 mm, package mechanical data ). blank option removed under plating technology in table 17: ordering information scheme . small text changes. 25-sep-2009 8 section 2.5.2: power-up conditions and section 2.5.3: device reset updated. figure 4: maximum rp value versus bus parasitic capacitance (c) for an i2c bus modified. t ns modified in table 11: input parameters . i cc and v il test conditions extended in table 12: dc characteristics (for temperature range 1 devices) . table 18. document revision history (continued) date revision changes
m34e02 doc id 10367 rev 8 33/33 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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